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What is SRAM 5:07
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In-Memory Computing 11:37
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14.2.2 SRAM 6:59
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In Memory Computing For Srams Information Guide

  1. Background to In Memory Computing For Srams
  2. Core Information
  3. History
  4. Deep Dive
  5. Future Outlook

Background to In Memory Computing For Srams

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Core Information

What is In-Memory Computing Guide
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History

[ZS2] SRAM-based In-Memory Computing for Energy-Efficient AI Systems Guide
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DAC YF Presentation - A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
DAC YF Presentation - A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
AI’s Hardware Problem
AI’s Hardware Problem
What is SRAM
What is SRAM
New in-memory computing SRAM with 90% bitline activity reduction, 109 TOPS/mm2 and 749-1,459 TOPS/W
New in-memory computing SRAM with 90% bitline activity reduction, 109 TOPS/mm2 and 749-1,459 TOPS/W
Comp. Arch. - Guest Lec.: In-Memory Computing: Memory Devices & Applications (ETH Zürich, Fall 2020)
Comp. Arch. - Guest Lec.: In-Memory Computing: Memory Devices & Applications (ETH Zürich, Fall 2020)
In-Memory Computing
In-Memory Computing
2025-08: Huimin Zheng(MPhil)- Mixed-Precision In-Memory Computing SRAM Macro Based on Charge Sharing
2025-08: Huimin Zheng(MPhil)- Mixed-Precision In-Memory Computing SRAM Macro Based on Charge Sharing
L12 In memory computing
L12 In memory computing
SRAM-based Compute-in-Memory AI ASICs : Apple M4 Chip
SRAM-based Compute-in-Memory AI ASICs : Apple M4 Chip
Hybrid RRAM/SRAM In-Memory Computing for Robust DNN Acceleration
Hybrid RRAM/SRAM In-Memory Computing for Robust DNN Acceleration
14.2.2 SRAM
14.2.2 SRAM

Deep Dive

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Last Updated: August 23, 2026

Future Outlook

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